10. CACHE Instructions
10.18 Index Load Data (D)
Index Load Data (D) loads a singleword of data and the corresponding four bits of byte parity into CP0 TagLo and ECC. The address of the target singleword is VA[13:2] of the CACHE instruction. The way of the target singleword is VA[0] of the CACHE instruction. The singleword of data will be loaded into the CP0 TagLo register. The byte parity will be loaded into CP0 ECC[3:0] register. The tag field is not read.
Parity checking is suppressed during operation of Index Load Data (D).
Copyright 1995, MIPS Technologies, Inc. -- 29 JAN 96
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